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About This Role
The Hardware Design, Rack-scale Technology and Platforms (HDRTP) engineering team designs, develops, validates, and delivers the hardware platforms that power Meta's AI and HPC infrastructure, deployed in data centers worldwide. Our designs are published for industry adoption through the Open Compute Project Foundation.We are seeking a senior AI Accelerator Module Design Engineer to serve as the technical owner for the electrical and PCB design of accelerator modules supporting Meta's custom silicon (MTIA) and third-party AI accelerators. This is a lead individual-contributor role: you will own module-level electrical architecture end to end from requirements definition and ASIC package-to-board co-design through schematic, stackup, power delivery, bring-up, and volume production across multiple concurrent programs and silicon generations.You will define the design methodologies, reference architectures, and design-rule standards that other engineers and ODM partners build against; resolve the hardest cross-domain trade-offs between signal integrity, power integrity, thermal, mechanical, and cost; and influence ASIC and rack-level architecture decisions upstream of the module. You will operate with minimal direction in an ambiguous, fast-moving environment, and will mentor and raise the technical bar for PCB and module engineers across the team.
Hardware Engineer, AI Accelerator Module Design Responsibilities:
- Own the end-to-end electrical architecture and PCB design of AI accelerator modules for high-performance, high-power, high-efficiency custom silicon (MTIA) and third-party accelerators
- Define module requirements and specifications in partnership with ASIC, platform, rack, and systems architecture teams
- translate system-level targets into implementable board-level design intent
- Lead ASIC package-to-board co-design, including breakout routing strategy, substrate and interposer interaction, and escape feasibility analysis for high pin-count, high-bandwidth devices
- Architect power delivery networks for extreme-current loads (multi-hundred-amp rails), owning DC-DC topology and architecture trade-offs (performance, transient response, efficiency, area, cost), decoupling strategy, and plane/stackup partitioning
- Drive high-speed interface design across PCIe Gen5/Gen6, CXL, UCIe, DDR5/LPDDR, HBM, NVLink/scale-up fabrics, and Ethernet up to 800G, including simulation-guided stackup and channel budgeting
- Set the technical direction for SI/PI methodology in partnership with Signal and Power Integrity teams
- define correlation strategy between simulation and measured silicon
- Define and own module-level design reviews
- set the quality bar for schematic, layout, and DFM/DFT readiness across internal designs and ODM-executed designs
- Lead board and silicon bring-up and own root-cause analysis of the most complex electrical, power, and interoperability failures
- drive corrective design action to closure
- Drive ODM/JDM partners through full NPI-to-mass-production cycles, holding partners to Meta design standards and schedule
- Develop reusable reference designs, design-rule libraries, and design automation that scale across programs and generations
- publish and champion designs through the Open Compute Project
- Evaluate and qualify leading-edge technologies with industry partners — HDI and advanced substrates, embedded components, novel materials, co-packaged and coherent optics — and build the business case for adoption
- Identify cross-organizational problems and lead XFN efforts to resolution without being asked
- influence decisions outside your direct scope through technical credibility rather than authority
- Mentor and develop PCB/module design engineers
- contribute to hiring, calibration of technical standards, and team-wide best practices
Minimum Qualifications:
- BS in Electrical Engineering, Computer Engineering, or a related technical discipline
- 10+ years of experience in electrical and PCB design for high-speed, high-power digital systems (servers, accelerators, networking, or HPC)
- Demonstrated experience as the lead engineer taking multiple complex custom board or module designs from concept through volume production
- Expert-level proficiency with EDA tools for schematic capture and PCB design (Cadence Allegro/OrCAD, Altium Designer, or equivalent)
- Deep expertise in high-speed digital interface design (PCIe, CXL, DDR4/DDR5, HBM, Ethernet 25G–800G) and SerDes-based channel design, including stackup and channel budgeting trade-offs
- Deep expertise in power delivery network architecture for high-current loads, including DC-DC topology selection, transient and efficiency analysis, and plane/decoupling strategy
- Experience with ASIC or GPU package-to-board co-design and breakout routing for high pin-count devices
- Experience leading board and silicon bring-up, debug, and failure analysis using oscilloscopes, VNAs, TDR, and power analyzers
- Experience owning technical direction across multiple concurrent programs and influencing decisions across hardware, firmware, mechanical, thermal, and manufacturing organizations
- Experience driving external ODM/JDM or component partners through design and production cycles
- Experience communicating technical trade-offs and recommendations in writing and verbally to engineering leadership
Preferred Qualifications:
- MS or PhD in Electrical Engineering with emphasis on electromagnetics, signal integrity, or power electronics
- Track record of establishing design standards or methodologies adopted at organizational scale
- Experience defining design automation and verification flows (Python, SKILL/LISP, or equivalent) adopted beyond their own program
- Experience designing accelerator modules for custom in-house silicon, including involvement in silicon requirements definition
- Experience with next-generation interconnect: PCIe Gen6/Gen7, CXL 3.x, UCIe, scale-up fabrics, or co-packaged/coherent optics
- Experience with HDI, rigid-flex, embedded component, and advanced substrate technologies, including vendor capability development
- Hands-on expertise with SI/PI simulation and correlation tools (Ansys HFSS, Cadence Sigrity, Keysight ADS/PathWave, or equivalent)
- Contributions to open-source hardware or the Open Compute Project, or external technical publications and standards-body participation
- 15+ years of experience in module or board design for AI/ML accelerators, data center, or HPC hardware
- Experience with liquid-cooled and thermally-constrained module design, including thermal-aware placement and stackup techniques
About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
$173,000/year to $245,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Salary Context
This $173K-$245K range is above the median for AI/ML Engineer roles in our dataset (median: $176K across 1540 roles with salary data).
View full AI/ML Engineer salary data →Role Details
About This Role
AI/ML Engineers build and deploy machine learning models in production. They work across the full ML lifecycle: data pipelines, model training, evaluation, and serving infrastructure. The role has evolved significantly over the past two years. Where ML Engineers once spent most of their time on model architecture, the job now tilts heavily toward inference optimization, cost management, and integrating LLM capabilities into existing systems. Companies want engineers who can ship production systems, and the experimenter-only role is fading fast.
Day-to-day, you're writing training pipelines, debugging data quality issues, setting up evaluation frameworks, and figuring out why your model performs differently in staging than it did on your dev set. The best ML engineers are obsessive about reproducibility and measurement. They instrument everything. They know that a model is only as good as the data feeding it and the infrastructure serving it.
Across the 9,653 AI roles we're tracking, AI/ML Engineer positions make up 76% of the market. At Meta, this role fits into their broader AI and engineering organization.
Demand for AI/ML Engineers has been strong and consistent. Unlike some AI roles that spike with hype cycles, ML engineering is a foundational need. Every company deploying AI models needs people who can keep them running, and the gap between research prototypes and production systems keeps growing.
What the Work Looks Like
A typical week might include: debugging a data pipeline that's silently dropping 3% of training examples, running A/B tests on a new model version, writing documentation for a feature flag system that lets you roll back model deployments, and reviewing a junior engineer's PR for a new evaluation metric. Meetings tend to be cross-functional since ML touches product, engineering, and data teams.
Demand for AI/ML Engineers has been strong and consistent. Unlike some AI roles that spike with hype cycles, ML engineering is a foundational need. Every company deploying AI models needs people who can keep them running, and the gap between research prototypes and production systems keeps growing.
Skills Required
Python and PyTorch dominate the requirements. Most roles expect experience with cloud platforms (AWS, GCP, or Azure) and familiarity with ML frameworks like TensorFlow or JAX. RAG (Retrieval-Augmented Generation) has become a top-3 skill requirement as companies integrate LLMs into their products. Docker and Kubernetes show up in about a third of postings, reflecting the production focus of the role.
Beyond the core stack, employers increasingly want experience with experiment tracking tools (MLflow, Weights & Biases), feature stores, and vector databases. Fine-tuning experience is valuable but less common than you'd think from reading Twitter. Most production LLM work is RAG and prompt engineering, not fine-tuning. If you have both, you're in a strong position.
Companies that are serious about AI/ML hiring tend to post specific infrastructure details in the job description: the frameworks they use, their model serving stack, their data pipeline tools. Vague postings that just say 'ML experience required' without specifics are often companies that haven't figured out what they need yet.
Compensation Benchmarks
AI/ML Engineer roles pay a median of $212,000 based on 11,857 positions with disclosed compensation. Mid-level AI roles across all categories have a median of $193,200. Disclosed range: $173K to $245K.
Across all AI roles, the market median is $213,400. Top-quartile compensation starts at $264,230. The 90th percentile reaches $319,400. For comparison, the highest-paying categories include AI Safety ($253,100) and Research Engineer ($252,000). By seniority level: Entry: $110,408; Mid: $193,200; Senior: $228,700; Director: $272,275; VP: $235,000.
Meta AI Hiring
Meta has 50 open AI roles right now. They're hiring across AI/ML Engineer, AI Safety, AI Software Engineer, Research Engineer. Positions span New York, NY, US, Menlo Park, CA, US, Santa Clara, CA, US. Compensation range: $152K - $361K.
Location Context
Across all AI roles, 6% (568 positions) offer remote work, while 9,010 require on-site attendance. Top AI hiring metros: New York (2,878 roles, $221,000 median); San Francisco (2,413 roles, $264,500 median); Los Angeles (1,340 roles, $210,000 median).
Career Path
Common paths into AI/ML Engineer roles include Data Scientist, Software Engineer, Research Engineer.
From here, career progression typically leads toward ML Architect, AI Engineering Manager, Principal ML Engineer.
The fastest path into ML engineering is through software engineering with a self-directed ML education. A CS degree helps, but production engineering skills matter more than academic credentials. Build something that works, deploy it, and measure it. That portfolio project is worth more than a Coursera certificate. For career growth, the fork comes around the senior level: go deep on technical complexity (staff/principal track) or move into managing ML teams.
What to Expect in Interviews
Expect system design questions around ML pipelines: how you'd build a training pipeline for a specific use case, handle data drift, or design A/B testing infrastructure for model deployments. Coding rounds typically involve Python, with emphasis on data manipulation (pandas, numpy) and algorithm implementation. Take-home assignments often ask you to build an end-to-end ML pipeline from raw data to deployed model.
When evaluating opportunities: Companies that are serious about AI/ML hiring tend to post specific infrastructure details in the job description: the frameworks they use, their model serving stack, their data pipeline tools. Vague postings that just say 'ML experience required' without specifics are often companies that haven't figured out what they need yet.
AI Hiring Overview
The AI job market has 9,653 open positions tracked in our dataset. By seniority: 193 entry-level, 4,500 mid-level, 3,455 senior, and 1,505 leadership roles (Director, VP, C-Level). Remote roles make up 6% of the market (568 positions). The remaining 9,010 roles require on-site or hybrid attendance.
The market median for AI roles is $213,400. Top-quartile compensation starts at $264,230. The 90th percentile reaches $319,400. Highest-paying categories: AI Safety ($253,100 median, 57 roles); Research Engineer ($252,000 median, 419 roles); AI Engineering Manager ($251,622 median, 51 roles).
Demand for AI/ML Engineers has been strong and consistent. Unlike some AI roles that spike with hype cycles, ML engineering is a foundational need. Every company deploying AI models needs people who can keep them running, and the gap between research prototypes and production systems keeps growing.
The AI Job Market Today
The AI job market spans 9,653 open positions across 16 role categories. The largest categories by volume: AI/ML Engineer (7,301), Data Scientist (441), AI Software Engineer (438). These three account for the majority of open positions, though smaller categories often have higher per-role compensation because of specialized skill requirements.
The seniority mix tells a story about where AI teams are in their maturity. Entry-level roles (193) are outnumbered by mid-level (4,500) and senior (3,455) positions, reflecting that most companies are past the 'build a team from scratch' phase and need experienced engineers who can ship production systems. Leadership roles (Director, VP, C-Level) total 1,505 positions, representing the bottleneck between technical execution and organizational strategy.
Remote work availability sits at 6% of all AI roles (568 positions), with 9,010 requiring on-site or hybrid attendance. The remote share has stabilized after the post-pandemic correction. Senior and specialized roles (Research Scientist, ML Architect) are more likely to be remote-eligible than entry-level positions, partly because experienced hires have more negotiating power and partly because these roles require less hands-on mentorship.
AI compensation is structured in clear tiers. The market median sits at $213,400. Top-quartile roles start at $264,230, and the 90th percentile reaches $319,400. These figures include base salary with disclosed compensation. Total compensation (including equity, bonuses, and sign-on) runs 20-40% higher at companies that offer those components.
Category matters for compensation. AI Safety roles lead at $253,100 median, while Prompt Engineer roles sit at $141,440. The spread between highest and lowest-paying categories reflects the premium on specialized technical skills versus broader analytical roles.
The most in-demand skills across all AI postings: Python (1,605 postings), Aws (916 postings), Azure (724 postings), Rag (634 postings), Gcp (522 postings), Pytorch (495 postings), Kubernetes (384 postings), Claude (383 postings). Python dominates, appearing in the vast majority of role descriptions regardless of category. Cloud platform experience (AWS, GCP, Azure) is the second most common requirement. The newer entrants to the top skills list (RAG, vector databases, LLM APIs) reflect the shift from traditional ML toward generative AI applications.
Frequently Asked Questions
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